M31 and Ambiq Cut Leakage Power by About 50% With New TSMC N12e Foundation IP for Edge AI Chips
M31 Technology and Ambiq have co-developed foundation IP for TSMC’s N12e process that cuts standard-cell leakage power by about 50%. It’s the kind of gain that decides whether a wearable lasts a day or a week.
N12e is TSMC’s 12nm platform for low-power and IoT chips. It’s a mature node where cost and battery life matter more than raw speed. Ambiq builds ultra-low-power chips for always-on devices like smartwatches, hearing aids and sensors, and it needed building blocks tuned to its own power targets.
What M31 built
M31 supplied two pieces. The first is a standard-cell library optimized for low power, where the joint design work produced the roughly 50% leakage cut. The second is an ultra-low-leakage single-port SRAM memory compiler with redundancy, power gating and built-in self-test. Its dual-rail design reaches close to 500 MHz with the periphery running near threshold voltage. Retention leakage stays within 1.05 to 1.1 times that of the bit cells themselves, so sleeping memory costs almost nothing.
Why foundation IP matters
Most chip power talk focuses on the processor. For always-on devices, though, leakage (the current a chip draws while doing nothing) is often where the battery goes. That’s decided in the standard cells and SRAM, the lowest layers of the design.
“Energy efficiency must be a focus starting from the foundation of a system-on-chip, especially as edge devices take on increasingly sophisticated AI workloads,” says Scott Hanson, Ambiq’s founder and CTO.
Jayanta Lahiri, vice president at M31, says designers are being asked “to hit unprecedented energy and area targets while still delivering meaningful compute and responsiveness.”
Wearables and AIoT devices are adding on-device AI while their batteries stay the same size. Savings at the transistor level are one of the few places left to find the extra power.